DDR3/4 Combo 10 Library Design in 28NM CMOS Technology
Abstract
This paper presents a DDR3 and DDR4 dual mode combo IO library containing half duplex combo transceiver, a separate calibration cell for ZQ calibration and Power/GNDcells with RC clamp for ESD protection in 28nm CMOS technology. The presented transceiver achieves 2166MT/s for DDR3 at 1.SV for two dual rank UDIMMs/channel and 2400MT/s for DDR4 at 1.2V for a single dual rank UDIMM. The embedded break before make functionality in the transmitter demonstrates a 17% reÂduction in crow-bar current at 2166MT/s.The slew rate control functionality demonstrates feasibilÂity in reducing reflection on an under-damped channel as well as reducing simultaneous-switch ing-output noise. The ESD protection is targeted for 2KV-HBM,8KV-MM& SA COM. The transmitter consumes a total power of 7.SmW/[email protected] and 5.8mW/[email protected] with a break before make a non-overlap delay of 60ps. Each cell has a footprint of 30µmx200µ and results in a continuously abutted structure when placed side by side.
KEYWORDS
SSTL, HSTL, POD, DDR3, DDR4, combo 10, multi-mode PHY, ZQ Calibration, Self-Biased Receiver, DIMM modeling, 28nm CMOS.
References
Jaejun Lee,et.al.,"Architecture of aMulti-slot Main Memory System for 3.2 Gbps Operation''.Circuits and Systems (ISCAS) proceedings of IEEE International Symposium 2010.
A Amirkhany, et al ''A 12.8-Gbls/ /ink Tri-Modal Single-Ended Memory Interface, IEEE Journal of Solid-State
Circuits,2012.
Min-Sun Keel et.al., "ESD-Resi/ien t Active Biasing Scheme for high-speed SSTL /Os''. Electrical Overstress/ Electrostatic Discharge symposium (EOS!ESD),2013.
A, Amirkhany, et.Al., "On overcoming the /imitationsof single-ended signaling for graphics memory interfaces'; Asian Solid-State Circuits Conference, 2011.
Seung-Jun Bae, et al''A 40nm 2Gb 7Gb!s/ pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock tracking BW IEEE Solid-State Cirrnits Conference Digest of Technical Papers (JSSCCJ, 2011.
Tzu-Chien Hsueh, etal "26.4A 25.6Gb/s differential and DDR4/ GDDR5 dual mode transmit ter with digital clock calibration in 22nm CMOS" IEEE So/id-State Circuits Conference Digest of Technical Papers (JSSCC), 2014.
EschJr, Gerald, and Tom Chen. "Near-linear CMOS 110 driver with Jess sensitivity to process, voltage, and temperaturevariations:' IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 2004
Sim, Jae-Yoon. "Circuit Design of DRAM for Mobile Generation." Journal of Semiconductor Technology and Science,2007.
Rex Khoet a/. "75nm7Gb!s!pin 1GbGDDR5 graphics memory devicewith bandwidth-improvemen ttechniques" Solid State Circuits Conference- Digest of Technical Papers, 2009.
JEDEC DDR3 SDRAM STANDARD, JESD79-3D, July 2012.
JEDEC DDR4 SDRAM STANDARD, JESD79-4. September 2012.
B.A. Chappell et. al., "Fast CMOS ECL receivers with 100-mV worst-case sensitivity" IEEE Journal of Solid-State Circuits, Feb 1988.
M. Bazes, "Two novel fully complementary self-biased CMOS differential amplifiers",IEEE Journal of Solid-State Circuits, Feb 1991.
TSMCESD Design Guide in 28nm HPM, 2012.
Steven Vo/dman, ''ESD :Design and Synthesis John Wiley & Sons 2011.
Design Ware DDR4 multiPHY Datasheet from Synopsys Inc.,2013.
JEDEC Standard on DDR3 SDRAM Un-buffered DIMM Design Specification
Design Guidefor Two DDR3- 1033 UDIMM Systems from Micron Inc.
DDR3 SDRAM Memory Interface Termination and Layout Guidelines from Altera Inc.
TN-41-13:DDR3 Point to Point Design Support from Micron Inc.
AMP single line model data-sheet (http://www.te.com)
DDR3 DIMM Sockets Catalog from Tyco Electronics.
Huimin He, Fengman Liu et al, "Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory"; Taylor and Francis Fiber and Integrated Optics Journal, Volume 35, pg. 212-229, 2016.
Jeongsik Yoo, Yeonho Lee,Yoonjae Choi,''A Low-Power Post-LPDDR4 Interface Using AC Termination at RXand an Active Inductor at TX"; IEEE Transactions on Circuits and Systems II: Express Briefs, Issue 99, pg. 1,September 2017.
Martin Brox, Mani Balakrishnan,Martin Broschwitz, Cristian Chetreanu et al, "An 8-Gb 12-Gbls/pin GDDR5X DRAM for Cost-Effective High-Performance Applications"; IEEE Journal of Solid State Cirrnits, Vol. 53, Issue 1, January 2018.
Hyun-Wook Lim, Sung Won Choi, Jeong-Keun Ahn et al, ''A 5.8-Gb!s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface; IEEE Journal of Solid State Circuits, Vol. 52, Issue 6,June 2017
